Operational amplifiers (opamps) are very widely used analog components. Their versatility makes them a building block for several applications. Typically, opamps exhibit certain limitations, the most important of which is the offset voltage. The offset voltage of an opamp is the differential voltage required to be applied at the input of the opamp to produce a null output. Many applications require the cancellation/minimization of the offset voltage.
There are a few well-known approaches to reduce/cancel the input referred offset or the effect of input referred offset in the opamps. If the opamp is used in the switched capacitor circuit, then offset voltage is stored in the capacitors connected to the input of the opamp during one phase of operation as discussed in “Analog MOS. Integrated Circuits for Signal Processing” by Rubik Gregorian and Gabor C. Temes. This is an effective technique, although it cannot be used in non-switched capacitor circuits.
There is a technique used in discrete opamp ICs, where an external potentiometer is used to nullify the offset voltage; but this technique needs two more pins, which is not an attractive approach when an opamp is just a part of a big chip with limited pin-outs. The third technique involves the input differential pair, the load transistors and current mirrors being sized and laid out in a matching fashion. The final offset voltage is determined by the difference in threshold voltages of the input differential pair and the active load devices, the gate area mismatch of the input differential and load devices, and the mismatch in the effective gate-source voltage of the input differential pair as discussed in “Analysis and design of Analog Integrated Circuits” by Paul R. Gray and Robert G. Meyer. The random mismatch in the currents in the gain and the load devices of the second stage of a two-stage opamp would further add up to the offset voltage.
To accurately determine and guarantee the offset voltage during design phase, it is necessary to know the precise analog characterization of the process which determines the mismatch of the parameters against different gate area, gate voltage, drain current, distance between the components in the layout etc. Unfortunately, pure digital CMOS processes do not characterize these values. Most ICs today are manufactured with large digital sections and some analog functionality. For economic viability, most of these chips are targeted on cheap CMOS digital processes. As an integral building block of analog circuitry, the demand for accurate opamps, which are not used in the switched capacitor circuits, is on the rise. Therefore, there is a need to develop a technique to produce opamps with input offset voltage guaranteed within a limit.
EP 1104092/U.S. Pat. No. 6,262,625 describes a method for reducing offset voltage by adjusting the body-bias (VB) of input pair MOS and transconductance (gm) of the load pair by DAC (digital to analog converter). Nwell only CMOS process cannot provide separate VB control of the NMOS input pair. So only the PMOS input pair OPAMP is possible, or else a costly process option (e.g. isolated PWELL) would be needed. Separate DAC requires extra constant consumption.
U.S. Pat. No. 4,356,450 defines a technique for eliminating offset voltage by adding Offset voltage/current to one of the input terminals by DAC/DAC+Voltage-to-current-converter (V2I). A separate DAC, extra comparator and opamp (for V2I) are needed, and it suffers from consumption and area overhead. Also, U.S. Pat. No. 4,933,643 proposes a method where the offset is cancelled by introducing a current imbalance at the input level shifter or the cascoded loads. It starts by introducing a deliberate offset in one direction and cancels that one; and, for any mismatch, if the offset is in the other direction it cannot be cancelled. This method also suffers from constant consumption in the current divider, which does not contribute to the opamp.